1. Technical Field
The present invention relates generally to semiconductor devices and methods of fabricating the same, and, more particularly, to semiconductor devices having a planarized insulating layer and methods of fabricating the same.
2. Discussion of the Related Art
Generally, a PRAM (phase-change random access memory) has a phase-change pattern and an interconnection layer pattern running across an active region within a range of a given design rule. The interconnection layer pattern is disposed on and is in contact with the phase-change pattern. The phase-change pattern includes a GST (GexSeyTez) material. The interconnection layer pattern may comprise tungsten (W). The interconnection layer pattern is in contact with the phase-change pattern through a contact hole.
However, in such a PRAM, a contact hole may expose sidewalls of the phase-change pattern with the design rule of the PRAM reduced. This means it may be more difficult to align the contact hole on the phase-change patterns within a range of the reduced design rule. This is because the phase-change pattern and the contact hole are also reduced in their sizes within a range of the reduced design rule. For this reason, the contact hole may be disposed so as to expose the sidewalls of the phase-change pattern. After the contact hole is formed, a CVD (chemical vapor deposition) process using a tungsten fluoride (WFx) gas may be performed on the contact hole. In the CVD process, the gas reacts with the phase-change pattern to vaporize the GST material, without forming a W layer filling the contact hole.
Further, an MRAM (magnetic random access memory) has a magnetic tunnel junction pattern and an interconnection layer pattern running across an active region within a range of a given design rule. The interconnection layer pattern is disposed on and is in contact with the magnetic tunnel junction pattern. The magnetic tunnel junction pattern has a magnetic tunnel junction layer pattern. The magnetic tunnel junction layer pattern may include a diamagnetic material layer (e.g. PtxMny layer) as well as a ferromagnetic material layer (e.g. NixFey layer), a dielectric layer (e.g. AlxOy layer), and a spin fixed layer (e.g. CoxFey layer), which are sequentially disposed in stack. The interconnection layer pattern may comprise tungsten (W). The interconnection layer pattern is in contact with the magnetic tunnel junction pattern through a contact hole.
Like the PRAM, the MRAM may have tungsten filling the contact hole to overcome an aspect ratio of the contact hole. The tungsten is formed by using a CVD process using a tungsten fluoride (WFx) gas. The CVD process is performed at a temperature of about 350° C. or higher, which may increase resistance of the magnetic tunnel junction layer pattern. This may result in decreasing a current sensing margin being capable of reading data of a selected cell inside an active region, and losing magnetic characteristics of the magnetic tunnel junction layer pattern.
On the other hand, Japan Patent Publication No. 2001-36026 to Kanetani Hiroyuki, et al discloses a semiconductor device and method of forming thereof. According to Kanetani Hiroyuki, et al., a semiconductor device and method of forming thereof includes a ferroelectric capacitor disposed in a semiconductor substrate. The ferroelectric capacitor includes a lower platinum (Pt) layer, a PZT (PbZr1-xTiO) layer and an upper platinum (Pt) layer, which are sequentially disposed in stack.
The ferroelectric capacitor is surrounded by a hydrogen barrier layer. The hydrogen barrier layer is formed to cover the ferroelectric capacitor downward from an upper portion of the semiconductor substrate. This is to minimize the hydrogen ions coming into the ferroelectric capacitor during semiconductor fabrication processes. Then, an interlayer insulating layer is formed to cover the hydrogen banner layer.
The semiconductor device and the method of forming thereof further include an interconnection line being in contact with the ferroelectric capacitor. The interconnection line penetrates the interlayer insulating layer and the hydrogen barrier layer, and is disposed on the upper platinum layer of the ferroelectric capacitor.
However, in the semiconductor device and the method of forming thereof, a contact hole may be formed in the interlayer insulating layer and the hydrogen barrier layer to make the interconnection line and the upper platinum layer be in contact with each other. The contact hole may not expose the upper platinum layer within a range of a reduced design rule. This may deteriorate electrical characteristics of the semiconductor device.